[slang] Testing error when switching to slang master branch

[dinoruic]

Hi all,

when building with the latest slang master branch, there seems to be an issue with tests on basic.sv.

Specifically, I'm getting the following unexpected output

$ circt-translate --import-verilog test/Conversion/ImportVerilog/basic.sv | FileCheck test/Conversion/ImportVerilog/basic.sv

../test/Conversion/ImportVerilog/basic.sv:1740:12: error: CHECK: expected string not found in input
 // CHECK: [[V0:%.+]] = moore.extract_ref %z3 from 2
           ^
<stdin>:1431:36: note: scanning from here
 %11 = moore.extract_ref %z3 from 1 : <l3> -> <l1>
                                   ^
<stdin>:1435:2: note: possible intended match here
 %15 = moore.extract_ref %w3 from 0 : <l2> -> <l1>
 ^

Input file: <stdin>
Check file: ../test/Conversion/ImportVerilog/basic.sv

-dump-input=help explains the following input dump.

Input was:
<<<<<<
              .
              .
              .
           1426:  %z3 = moore.net wire : <l3> 
           1427:  %w3 = moore.net wire : <l2> 
           1428:  %8 = moore.read %x3 : <l1> 
           1429:  %9 = moore.read %y3 : <l1> 
           1430:  %10 = moore.extract_ref %z3 from 0 : <l3> -> <l1> 
           1431:  %11 = moore.extract_ref %z3 from 1 : <l3> -> <l1> 
check:1740'0                                        X~~~~~~~~~~~~~~~ error: no match found
           1432:  %12 = moore.read %z3 : <l3> 
check:1740'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           1433:  %13 = moore.constant 2 : i32 
check:1740'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           1434:  %14 = moore.dyn_extract %12 from %13 : l3, i32 -> l1 
check:1740'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           1435:  %15 = moore.extract_ref %w3 from 0 : <l2> -> <l1> 
check:1740'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
check:1740'1      ?                                                  possible intended match
           1436:  %16 = moore.read %w3 : <l2> 
check:1740'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           1437:  %17 = moore.constant 1 : i32 
check:1740'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           1438:  %18 = moore.dyn_extract %16 from %17 : l2, i32 -> l1 
check:1740'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           1439:  %p3.v1, %p3.c1 = moore.instance "p3" @MultiPorts(a0: %8: !moore.l1, a1: %9: !moore.l1, v0: %14: !moore.l1, v2: %10: !moore.ref<l1>, c0: %18: !moore.l1) -> (v1: !moore.l1, c1: !moore.l1) 
check:1740'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           1440:  moore.assign %11, %p3.v1 : l1 
check:1740'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
              .
              .
              .
>>>>>>

It looks like moore.extract_ref %z3 from 2 is missing but therefore we have this:

%12 = moore.read %z3 : <l3>
%13 = moore.constant 2 : i32
%14 = moore.dyn_extract %12 from %13 : l3, i32 -> l1 

Do you have any advice on how to proceed with this?

Thanks!

[fabianschuiki]

Hey @dinoruic, nice find! This looks like something about Slang's constant evaluation for bit/range selects like [a] and [a:b] changed. This is the ImportVerilog code that handles bit selects like [a]:

https://github.com/llvm/circt/blob/main/lib/Conversion/ImportVerilog/Expressions.cpp#L181-L184

It simply checks if a has a constant value. This is not guaranteed to be eagerly populated by Slang. In case Slang doesn't need the constant value for type checking, it will often not populate these constants. If that is the case, we can explicitly ask Slang to evaluate a constant. There is a evaluateConstant helper further down in that file:

https://github.com/llvm/circt/blob/main/lib/Conversion/ImportVerilog/Expressions.cpp#L2226-L2234

Instead of calling expr.selector().getConstant() in the bit select code, we might have to do evaluateConstant(expr.selector()) instead to ask for the constant to be evaluated. I'm pretty sure the same issue also exists for range selects, and in some other places in ImportVerilog.