[FIRRTL] Elide domains of zero-width ports in LowerDomains

[seldridge]

Consider the following example, directly adapted from an existing lower-domains.mlir test:

 firrtl.circuit "Foo" {
  firrtl.domain @ClockDomain
  firrtl.module private @ZeroWidthPort(
    in %A: !firrtl.domain of @ClockDomain,
    in %a: !firrtl.uint<0> domains [%A]
  ) {
  }
  firrtl.module @Foo() {}
}

Currently, this will lower the ZeroWidthPort module to the following. This keeps the domain information, but it is intentionally empty because LowerToHW will strip zero-width ports.

firrtl.module private @ZeroWidthPort(
  in %A: !firrtl.class<@ClockDomain()>, 
  out %A_out: !firrtl.class<@ClockDomain_out(
    in domainInfo_in: !firrtl.class<@ClockDomain()>, 
    out domainInfo_out: !firrtl.class<@ClockDomain()>, 
    in associations_in: !firrtl.list<path>, 
    out associations_out: !firrtl.list<path>
  )>, 
  in %a: !firrtl.uint<0>
) {
      %A_object = firrtl.object @ClockDomain_out(in domainInfo_in: !firrtl.class<@ClockDomain()>, out domainInfo_out: !firrtl.class<@ClockDomain()>, in associations_in: !firrtl.list<path>, out associations_out: !firrtl.list<path>)
      %0 = firrtl.object.subfield %A_object[domainInfo_in] : !firrtl.class<@ClockDomain_out(in domainInfo_in: !firrtl.class<@ClockDomain()>, out domainInfo_out: !firrtl.class<@ClockDomain()>, in associations_in: !firrtl.list<path>, out associations_out: !firrtl.list<path>)>
      firrtl.propassign %0, %A : !firrtl.class<@ClockDomain()>
      %1 = firrtl.object.subfield %A_object[associations_in] : !firrtl.class<@ClockDomain_out(in domainInfo_in: !firrtl.class<@ClockDomain()>, out domainInfo_out: !firrtl.class<@ClockDomain()>, in associations_in: !firrtl.list<path>, out associations_out: !firrtl.list<path>)>
      %2 = firrtl.list.create  : !firrtl.list<path>
      firrtl.propassign %1, %2 : !firrtl.list<path>
      firrtl.propassign %A_out, %A_object : !firrtl.class<@ClockDomain_out(in domainInfo_in: !firrtl.class<@ClockDomain()>, out domainInfo_out: !firrtl.class<@ClockDomain()>, in associations_in: !firrtl.list<path>, out associations_out: !firrtl.list<path>)>
    }

I've observed a handful of situations where there are private modules with lots of this going on, e.g., O(10) unused, inferred domains show up because there are lots of zero-width ports.

It would be better if truly unused domains could be stripped when they have no association information. This may motivate breaking the zero-width removal part of LowerToHW out to a pass that runs earlier in the FIRRTL to HW conversion pipeline.