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Add Zvzip extension for reordering structured data
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‎src/colophon.adoc‎

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@@ -62,6 +62,7 @@ h|Extension h|Version h|Status
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|*Zclsd* |*1.0* |*Ratified*
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|*B* |*1.0* |*Ratified*
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|*V* |*1.0* |*Ratified*
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|*Zvzip* |*0.1* |_Draft_
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|*Zbkb* |*1.0* |*Ratified*
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|*Zbkc* |*1.0* |*Ratified*
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|*Zbkx* |*1.0* |*Ratified*

‎src/riscv-unprivileged.adoc‎

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@@ -183,6 +183,7 @@ include::c-st-ext.adoc[]
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include::zc.adoc[]
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include::b-st-ext.adoc[]
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include::v-st-ext.adoc[]
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include::zvzip.adoc[]
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include::scalar-crypto.adoc[]
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include::vector-crypto.adoc[]
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include::unpriv-cfi.adoc[]

‎src/zvzip.adoc‎

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== "Zvzip" Extension for Reordering Structured Data, Version 0.1
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This chapter describes the Zvzip standard extension for reordering structured
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data in vector registers. These instructions address usages such as packing and
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unpacking data structures such as color components of a pixel, real and
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imaginary components of complex numbers, transposing small matrices, among
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others.
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[%autowidth]
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[%header,cols="2,4"]
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|===
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|Mnemonic |Instruction
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| vzip.vv | <<insns-vzip>>
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| vunzipe.v | <<insns-vunzipe>>
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| vunzipo.v | <<insns-vunzipo>>
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| vpaire.vv | <<insns-vpaire>>
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| vpairo.vv | <<insns-vpairo>>
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|===
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The Zvzip Extension depends on the Zve32x Extension.
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<<<
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[[insns-vzip, Vector Zip]]
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=== Vector Zip Instruction
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Synopsis::
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Interleave elements from source vector register groups into destination vector
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register groups.
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Mnemonic::
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vzip.vv vd, vs2, vs1, vm
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Encoding::
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[wavedrom, , svg]
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....
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{reg:[
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{bits: 7, name: 'OP-V'},
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{bits: 5, name: 'vd'},
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{bits: 3, name: 'OPMVV'},
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{bits: 5, name: 'vs1'},
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{bits: 5, name: 'vs2'},
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{bits: 1, name: 'vm'},
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{bits: 6, name: '111110'},
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], config:{lanes: 1, hspace:1024}}
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....
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Description::
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Vector Zip (VZIP) instruction interleaves elements from two source vector
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register groups (`vs2` and `vs1`) into one destination vector register group
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(`vd`) by alternating elements from the two sources. +
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+
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For destination element index `i`, if `i` is even then `vd[i] = vs2[i/2]`, and
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if `i` is odd then `vd[i] = vs1[i/2]`. +
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+
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Equivalently, the result order is:
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`vd = [vs2[0], vs1[0], vs2[1], vs1[1], ... ]` +
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+
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This instruction operates with an effective vector length (EVL) of 2*VL. The
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destination EMUL is 2xLMUL. The instruction is reserved when LMUL is 8.
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Prestart, inactive, and tail element handling follows the standard vector
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rules, applied over the EVL. +
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+
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The destination vector register group may overlap the source vector register
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group if the overlap is in the highest-numbered part of the destination
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register group and the source EMUL is at least 1. If the overlap violates these
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constraints, the instruction encoding is reserved.
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Operation::
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[source,sail]
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--
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function clause execute (VZIP(vs2, vs1, vd, vm)) = {
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EVL = 2 * VL;
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foreach (i from vstart to EVL-1) {
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let j = i / 2;
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let op1 = get_velem(vs1, SEW, j);
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let op2 = get_velem(vs2, SEW, j);
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let res = if (i % 2 == 0) then op2 else op1;
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if (vm == 0b1) | (v0[i] == 0b1) then
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set_velem(vd, EEW=SEW, i, res);
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// inactive element handling follows VMA
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}
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// tail element handling follows VTA
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RETIRE_SUCCESS
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}
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--
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<<<
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[[insns-vunzipe, Vector Unzip Even]]
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=== Vector Unzip Even Instruction
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Synopsis::
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Extract even-indexed elements from source vector register group into the
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destination vector register group.
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Mnemonic::
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vunzipe.v vd, vs2, vm
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Encoding::
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[wavedrom, , svg]
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....
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{reg:[
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{bits: 7, name: 'OP-V'},
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{bits: 5, name: 'vd'},
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{bits: 3, name: 'OPMVV'},
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{bits: 5, name: '01011'},
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{bits: 5, name: 'vs2'},
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{bits: 1, name: 'vm'},
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{bits: 6, name: '010010'},
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], config:{lanes: 1, hspace:1024}}
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....
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Description::
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The vector unzip-even instruction (VUNZIPE) extracts VL even-indexed elements
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from the source vector register group into the destination vector register
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group. +
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+
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This instruction accesses 2*VL elements in the source vector register group and
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the source EMUL is 2xLMUL. The instruction is reserved when LMUL is 8. +
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+
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Prestart, inactive, and tail element handling follow the standard vector
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rules and are defined over the destination element indices (`0` to `VL-1`). +
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+
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The destination vector register group may overlap the source vector register
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group only if the overlap is in the lowest-numbered part of the source register
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group. If the overlap violates these constraints, the instruction encoding is
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reserved.
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Operation::
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[source,sail]
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--
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function clause execute (VUNZIPE(vs2, vd, vm)) = {
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foreach (i from vstart to VL-1) {
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let j = i * 2;
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if (vm == 0b1) | (v0[i] == 0b1) then
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set_velem(vd, EEW=SEW, i, get_velem(vs2, SEW, j));
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// inactive element handling follows VMA
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}
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// tail element handling follows VTA
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RETIRE_SUCCESS
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}
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--
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<<<
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[[insns-vunzipo, Vector Unzip Odd]]
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=== Vector Unzip Odd Instruction
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Synopsis::
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Extract odd-indexed elements from source vector register group into the
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destination vector register group.
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Mnemonic::
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vunzipo.v vd, vs2, vm
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Encoding::
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[wavedrom, , svg]
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....
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{reg:[
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{bits: 7, name: 'OP-V'},
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{bits: 5, name: 'vd'},
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{bits: 3, name: 'OPMVV'},
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{bits: 5, name: '01111'},
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{bits: 5, name: 'vs2'},
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{bits: 1, name: 'vm'},
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{bits: 6, name: '010010'},
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], config:{lanes: 1, hspace:1024}}
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....
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Description::
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The vector unzip-odd instruction (VUNZIPO) extracts VL odd-indexed elements
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from the source vector register group into the destination vector register
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group. +
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+
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This instruction accesses 2*VL elements in the source vector register group and
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the source EMUL is 2xLMUL. The instruction is reserved when LMUL is 8. +
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+
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Prestart, inactive, and tail element handling follow the standard vector
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rules and are defined over the destination element indices (`0` to `VL-1`). +
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+
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The destination vector register group may overlap the source vector register
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group only if the overlap is in the lowest-numbered part of the source register
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group. If the overlap violates these constraints, the instruction encoding is
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reserved.
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Operation::
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[source,sail]
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--
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function clause execute (VUNZIPO(vs2, vd, vm)) = {
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foreach (i from vstart to VL-1) {
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let j = (i * 2) + 1;
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if (vm == 0b1) | (v0[i] == 0b1) then
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set_velem(vd, EEW=SEW, i, get_velem(vs2, SEW, j));
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// inactive element handling follows VMA
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}
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// tail element handling follows VTA
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RETIRE_SUCCESS
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}
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--
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<<<
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[[insns-vpaire, Vector Pair Even]]
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=== Vector Pair Even Instruction
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Synopsis::
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Interleave the even-indexed elements of the source vector register groups into
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the destination vector register group.
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Mnemonic::
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vpaire.vv vd, vs2, vs1, vm
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Encoding::
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[wavedrom, , svg]
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....
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{reg:[
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{bits: 7, name: 'OP-V'},
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{bits: 5, name: 'vd'},
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{bits: 3, name: 'OPIVV'},
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{bits: 5, name: 'vs1'},
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{bits: 5, name: 'vs2'},
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{bits: 1, name: 'vm'},
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{bits: 6, name: '001111'},
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], config:{lanes: 1, hspace:1024}}
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....
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Description::
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The vector pair-even instruction (VPAIRE) interleaves the even-indexed
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elements of the source vector register groups into the destination vector
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register group. +
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+
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For destination element index `i`, if `i` is even then `vd[i] = vs2[i]`, and if
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`i` is odd then `vd[i] = vs1[i - 1]`. +
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+
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Equivalently, the result order is:
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`vd = [vs2[0], vs1[0], vs2[2], vs1[2], ... ]` +
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+
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The destination vector register group cannot overlap the source vector register
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groups and, if masked, cannot overlap the mask register. If the overlap
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violates these constraints, the instruction encoding is reserved. +
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+
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Prestart, inactive, and tail element handling follow the standard vector rules.
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Operation::
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[source,sail]
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--
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function clause execute (VPAIRE(vs2, vs1, vd, vm)) = {
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foreach (i from vstart to VL-1) {
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let j = if (i % 2) == 0 then i else (i - 1);
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let res = if (i % 2) == 0
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then get_velem(vs2, SEW, j)
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else get_velem(vs1, SEW, j);
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if (vm == 0b1) | (v0[i] == 0b1) then
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set_velem(vd, EEW=SEW, i, res);
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// inactive element handling follows VMA
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}
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// tail element handling follows VTA
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RETIRE_SUCCESS
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}
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--
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<<<
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[[insns-vpairo, Vector Pair Odd]]
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=== Vector Pair Odd Instruction
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Synopsis::
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Interleave the odd-indexed elements of the source vector register groups into
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the destination vector register group.
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Mnemonic::
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vpairo.vv vd, vs2, vs1, vm
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Encoding::
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[wavedrom, , svg]
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....
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{reg:[
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{bits: 7, name: 'OP-V'},
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{bits: 5, name: 'vd'},
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{bits: 3, name: 'OPMVV'},
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{bits: 5, name: 'vs1'},
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{bits: 5, name: 'vs2'},
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{bits: 1, name: 'vm'},
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{bits: 6, name: '001111'},
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], config:{lanes: 1, hspace:1024}}
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....
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Description::
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The vector pair-odd instruction (VPAIRO) interleaves the odd-indexed
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elements of the source vector register groups into the destination vector
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register group. +
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+
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For destination element index `i`, if `i` is even then `vd[i] = vs2[i + 1]`, and
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if `i` is odd then `vd[i] = vs1[i]`. +
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+
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Equivalently, the result order is:
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`vd = [vs2[1], vs1[1], vs2[3], vs1[3], ... ]` +
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+
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The destination vector register group cannot overlap the source vector register
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groups and, if masked, cannot overlap the mask register. If the overlap
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violates these constraints, the instruction encoding is reserved. +
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+
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Prestart, inactive, and tail element handling follow the standard vector rules.
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+
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VPAIRO may read one element past `VL` in `vs2` when `VL` is odd. If the element
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index is greater than or equal to VLMAX in the source vector register group,
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the value 0 is returned for that element.
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Operation::
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[source,sail]
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--
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function clause execute (VPAIRO(vs2, vs1, vd, vm)) = {
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foreach (i from vstart to VL-1) {
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let j = if (i % 2) == 0 then (i + 1) else i;
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let res =
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if (j >= vlmax) then zeros()
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else if (i % 2) == 0 then get_velem(vs2, SEW, j)
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else get_velem(vs1, SEW, j);
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if (vm == 0b1) | (v0[i] == 0b1) then
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set_velem(vd, EEW=SEW, i, res);
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// inactive element handling follows VMA
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}
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// tail element handling follows VTA
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RETIRE_SUCCESS
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}
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--
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<<<
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[NOTE]
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====
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The following example illustrates use of the vector pair-even and pair-odd to
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transpose VL/4 independent 4x4 matrices packed across vector registers.
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The first stage operates on 32-bit elements. The second stage packs adjacent
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pairs into 64-bit elements to complete the transpose.
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----
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vsetivli t0, zero, e32, m1, ta, ma
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vpaire.vv v5, v1, v2 #|a|b|c|d|A|B|C|D|.. |a|e|c|g|A|E|C|G|..
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vpairo.vv v6, v1, v2 #|e|f|g|h|E|F|G|H|.. -> |b|f|d|h|B|F|D|H|..
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vpaire.vv v7, v3, v4 #|i|j|k|l|I|J|K|L|.. |i|m|k|o|I|M|K|O|..
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vpairo.vv v8, v3, v4 #|m|n|o|p|M|N|O|P|.. |j|n|l|p|J|N|L|P|..
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vsetivli t0, zero, e64, m1, ta, ma
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vpaire.vv v1, v5, v7 #|a e|c g|A E|C G|.. |a e|i m|A E|I M|..
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vpaire.vv v2, v6, v8 #|b f|d h|B F|D H|.. -> |b f|j n|B F|J N|..
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vpairo.vv v3, v5, v7 #|i m|k o|I M|K O|.. |c g|k o|C G|K O|..
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vpairo.vv v4, v6, v8 #|j n|l p|J N|L P|.. |d h|l p|D H|L P|..
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----
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====

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