Skip to content
Draft
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 0 additions & 6 deletions include/circt/Dialect/FIRRTL/AnnotationDetails.h
Original file line number Diff line number Diff line change
Expand Up @@ -161,12 +161,6 @@ constexpr const char *loadMemoryFromFileAnnoClass =
constexpr const char *loadMemoryFromFileInlineAnnoClass =
"firrtl.annotations.MemoryFileInlineAnnotation";

// WiringTransform Annotations
constexpr const char *wiringSinkAnnoClass =
"firrtl.passes.wiring.SinkAnnotation";
constexpr const char *wiringSourceAnnoClass =
"firrtl.passes.wiring.SourceAnnotation";

// Attribute annotations.
constexpr const char *attributeAnnoClass = "firrtl.AttributeAnnotation";

Expand Down
11 changes: 0 additions & 11 deletions include/circt/Dialect/FIRRTL/FIRRTLAnnotationHelper.h
Original file line number Diff line number Diff line change
Expand Up @@ -279,16 +279,6 @@ struct WiringProblem {
RefTypeUsage refTypeUsage;
};

/// A representation of a legacy Wiring problem consisting of a signal source
/// that should be connected to one or many sinks.
struct LegacyWiringProblem {
/// A source to wire from.
Value source;

/// Sink(s) to wire to.
SmallVector<Value> sinks;
};

/// A store of pending modifications to a FIRRTL module associated with solving
/// one or more WiringProblems.
struct ModuleModifications {
Expand Down Expand Up @@ -356,7 +346,6 @@ struct ApplyState {
bool noRefTypePorts;

DenseSet<InstanceOp> wiringProblemInstRefs;
DenseMap<StringAttr, LegacyWiringProblem> legacyWiringProblems;
SmallVector<WiringProblem> wiringProblems;

hw::InnerSymbolNamespace &getNamespace(FModuleLike module) {
Expand Down
1 change: 0 additions & 1 deletion lib/Dialect/FIRRTL/Transforms/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,6 @@ add_circt_dialect_library(CIRCTFIRRTLTransforms
InferWidths.cpp
InjectDUTHierarchy.cpp
InnerSymbolDCE.cpp
LegacyWiring.cpp
LinkCircuits.cpp
Lint.cpp
LayerMerge.cpp
Expand Down
103 changes: 0 additions & 103 deletions lib/Dialect/FIRRTL/Transforms/LegacyWiring.cpp

This file was deleted.

26 changes: 0 additions & 26 deletions lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -672,8 +672,6 @@ static llvm::StringMap<AnnoRecord> annotationRecords{{
{loadMemoryFromFileAnnoClass, {stdResolve, applyLoadMemoryAnno<false>}},
{loadMemoryFromFileInlineAnnoClass,
{stdResolve, applyLoadMemoryAnno<true>}},
{wiringSinkAnnoClass, {stdResolve, applyWiring}},
{wiringSourceAnnoClass, {stdResolve, applyWiring}},
{attributeAnnoClass, {stdResolve, applyAttributeAnnotation}}}};

LogicalResult
Expand Down Expand Up @@ -713,7 +711,6 @@ struct LowerAnnotationsPass

void runOnOperation() override;
LogicalResult applyAnnotation(DictionaryAttr anno, ApplyState &state);
LogicalResult legacyToWiringProblems(ApplyState &state);
LogicalResult solveWiringProblems(ApplyState &state);

SmallVector<DictionaryAttr> worklistAttrs;
Expand Down Expand Up @@ -758,26 +755,6 @@ LogicalResult LowerAnnotationsPass::applyAnnotation(DictionaryAttr anno,
return success();
}

/// Convert consumed SourceAnnotation and SinkAnnotation into WiringProblems,
/// using the pin attribute as newNameHint
LogicalResult LowerAnnotationsPass::legacyToWiringProblems(ApplyState &state) {
for (const auto &[name, problem] : state.legacyWiringProblems) {
if (!problem.source)
return mlir::emitError(state.circuit.getLoc())
<< "Unable to resolve source for pin: " << name;

if (problem.sinks.empty())
return mlir::emitError(state.circuit.getLoc())
<< "Unable to resolve sink(s) for pin: " << name;

for (const auto &sink : problem.sinks) {
state.wiringProblems.push_back(
{problem.source, sink, {}, WiringProblem::RefTypeUsage::Never});
}
}
return success();
}

/// Modify the circuit to solve and apply all Wiring Problems in the circuit. A
/// Wiring Problem is a mapping from a source to a sink that can be connected
/// via a base Type or RefType as requested. This uses a two-step approach.
Expand Down Expand Up @@ -1229,9 +1206,6 @@ void LowerAnnotationsPass::runOnOperation() {
++numFailures;
}

if (failed(legacyToWiringProblems(state)))
++numFailures;

if (failed(solveWiringProblems(state)))
++numFailures;

Expand Down
123 changes: 0 additions & 123 deletions test/Dialect/FIRRTL/legacy-wiring-errors.mlir

This file was deleted.

Loading